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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual Up Counters
The MC14518B dual BCD counter and the MC14520B dual binary counter are constructed with MOS P±channel and N±channel enhancement mode devices in a single monolithic structure. Each consists of two identical, independent, internally synchronous 4±stage counters. The counter stages are type D flip±flops, with interchangeable Clock and Enable lines for incrementing on either the positive±going or negative±going transition as required when cascading multiple stages. Each counter can be cleared by applying a high level on the Reset line. In addition, the MC14518B will count out of all undefined states within two clock periods. These complementary MOS up counters find primary use in multi±stage synchronous or ripple counting applications requiring low power dissipation and/or high noise immunity.
•Diode Protection on All Inputs
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•Internally Synchronous for High Internal and External Speeds
•Logic Edge±Clocked Design Ð Incremented on Positive Transition of Clock or Negative Transition on Enable
•Capable of Driving Two Low±power TTL Loads or One Low±power Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol |
Parameter |
Value |
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Unit |
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VDD |
DC Supply Voltage |
± 0.5 to + |
18.0 |
V |
Vin, Vout |
Input or Output Voltage (DC or Transient) |
0.5 to VDD + 0.5 |
V |
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Iin, Iout |
Input or Output Current (DC or Transient), |
± 10 |
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mA |
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per Pin |
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PD |
Power Dissipation, per Package² |
500 |
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mW |
Tstg |
Storage Temperature |
± 65 to + |
150 |
_C |
TL |
Lead Temperature (8±Second Soldering) |
260 |
|
_C |
* Maximum Ratings are those values beyond which damage to the device may occur. ²Temperature Derating:
Plastic ªP and D/DWº Packages: ± 7.0 mW/C From 65_C To 125_C
Ceramic ªLº Packages: ± 12 mW/C From 100_C To 125_C
TRUTH TABLE
Clock |
Enable |
Reset |
Action |
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1 |
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0 |
Increment Counter |
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0 |
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0 |
Increment Counter |
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X |
0 |
No Change |
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X |
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0 |
No Change |
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0 |
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0 |
No Change |
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1 |
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0 |
No Change |
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X |
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X |
1 |
Q0 thru Q3 = 0 |
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X = Don't Care
MC14518B
MC14520B
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
ORDERING INFORMATION
MC14XXXBCP |
Plastic |
MC14XXXBCL |
Ceramic |
MC14XXXBDW |
SOIC |
TA = ± 55° to 125°C for all packages.
BLOCK DIAGRAM
CLOCK |
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Q0 |
3 |
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1 |
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Q1 |
4 |
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C |
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2 |
Q2 |
5 |
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ENABLE |
R |
Q3 |
6 |
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7 |
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CLOCK |
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Q0 |
11 |
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9 |
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Q1 |
12 |
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C |
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10 |
Q2 |
13 |
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ENABLE |
R |
Q3 |
14 |
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15 |
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VDD = PIN 16
VSS = PIN 8
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
REV 3 1/94
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
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VDD |
± 55_C |
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25_C |
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125_C |
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Characteristic |
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Symbol |
Vdc |
Min |
Max |
Min |
Typ # |
Max |
Min |
Max |
Unit |
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Output Voltage |
ª0º Leve |
VOL |
5.0 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
Vdc |
Vin = VDD or 0 |
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10 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
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15 |
Ð |
0.05 |
Ð |
0 |
0.05 |
Ð |
0.05 |
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ª1º Leve |
VOH |
5.0 |
4.95 |
Ð |
4.95 |
5.0 |
Ð |
4.95 |
Ð |
Vdc |
Vin = 0 or VDD |
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10 |
9.95 |
Ð |
9.95 |
10 |
Ð |
9.95 |
Ð |
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15 |
14.95 |
Ð |
14.95 |
15 |
Ð |
14.95 |
Ð |
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Input Voltage |
ª0º Leve |
VIL |
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Vdc |
(VO = 4.5 or 0.5 Vdc) |
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5.0 |
Ð |
1.5 |
Ð |
2.25 |
1.5 |
Ð |
1.5 |
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(VO = 9.0 or 1.0 Vdc) |
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10 |
Ð |
3.0 |
Ð |
4.50 |
3.0 |
Ð |
3.0 |
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(VO = 13.5 or 1.5 Vdc) |
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15 |
Ð |
4.0 |
Ð |
6.75 |
4.0 |
Ð |
4.0 |
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(VO = 0.5 or 4.5 Vdc) |
ª1º Leve |
VIH |
5.0 |
3.5 |
Ð |
3.5 |
2.75 |
Ð |
3.5 |
Ð |
Vdc |
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(VO = 1.0 or 9.0 Vdc) |
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10 |
7.0 |
Ð |
7.0 |
5.50 |
Ð |
7.0 |
Ð |
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(VO = 1.5 or 13.5 Vdc) |
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15 |
11 |
Ð |
11 |
8.25 |
Ð |
11 |
Ð |
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Output Drive Current |
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IOH |
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mAdc |
(VOH = 2.5 Vdc) |
Source |
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5.0 |
± 3.0 |
Ð |
± 2.4 |
± 4.2 |
Ð |
± 1.7 |
Ð |
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(VOH = 4.6 Vdc) |
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5.0 |
± 0.64 |
Ð |
± 0.51 |
± 0.88 |
Ð |
± 0.36 |
Ð |
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(VOH = 9.5 Vdc) |
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10 |
± 1.6 |
Ð |
± 1.3 |
± 2.25 |
Ð |
± 0.9 |
Ð |
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(VOH = 13.5 Vdc) |
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15 |
± 4.2 |
Ð |
± 3.4 |
± 8.8 |
Ð |
± 2.4 |
Ð |
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(VOL = 0.4 Vdc) |
Sink |
IOL |
5.0 |
0.64 |
Ð |
0.51 |
0.88 |
Ð |
0.36 |
Ð |
mAdc |
(VOL = 0.5 Vdc) |
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10 |
1.6 |
Ð |
1.3 |
2.25 |
Ð |
0.9 |
Ð |
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(VOL = 1.5 Vdc) |
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15 |
4.2 |
Ð |
3.4 |
8.8 |
Ð |
2.4 |
Ð |
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Input Current |
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Iin |
15 |
Ð |
± 0.1 |
Ð |
± 0.00001 |
± 0.1 |
Ð |
± 1.0 |
μAdc |
Input Capacitance |
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Cin |
Ð |
Ð |
Ð |
Ð |
5.0 |
7.5 |
Ð |
Ð |
pF |
(Vin = 0) |
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Quiescent Current |
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IDD |
5.0 |
Ð |
5.0 |
Ð |
0.005 |
5.0 |
Ð |
150 |
μAdc |
(Per Package) |
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10 |
Ð |
10 |
Ð |
0.010 |
10 |
Ð |
300 |
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15 |
Ð |
20 |
Ð |
0.015 |
20 |
Ð |
600 |
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Total Supply Current**² |
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IT |
5.0 |
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IT = (0.6 μA/kHz) f + IDD |
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μAdc |
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(Dynamic plus Quiescent, |
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10 |
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IT = (1.2 μA/kHz) f + IDD |
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Per Package) |
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15 |
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IT = (1.7 μA/kHz) f + IDD |
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(CL = 50 pF on all outputs, all |
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buffers switching) |
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#Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance.
** The formulas given are for the typical characteristics only at 25_C. ²T o calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL ± 50) Vfk
where: IT is in μA (per package), CL in pF, V = (VDD ± VSS) in volts, f in kHz is input frequency, and k = 0.002.
PIN ASSIGNMENT
CA |
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1 |
16 |
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VDD |
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EA |
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2 |
15 |
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RB |
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Q0A |
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3 |
14 |
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Q3B |
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Q1A |
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4 |
13 |
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Q2B |
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Q2A |
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5 |
12 |
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Q1B |
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Q3A |
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6 |
11 |
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Q0B |
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RA |
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7 |
10 |
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EB |
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VSS |
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8 |
9 |
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CB |
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MC14518B MC14520B |
MOTOROLA CMOS LOGIC DATA |
410 |
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SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
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All Types |
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Characteristic |
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Symbol |
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VDD |
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Unit |
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Min |
Typ # |
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Max |
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Output Rise and Fall Time |
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tTLH, |
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ns |
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tTLH, tTHL = (1.5 ns/pF) CL + 25 ns |
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tTHL |
5.0 |
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Ð |
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100 |
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200 |
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tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns |
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10 |
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50 |
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100 |
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tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns |
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15 |
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40 |
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80 |
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Propagation Delay Time |
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tPLH, |
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ns |
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Clock to Q/Enable to Q |
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tPHL |
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tPLH, tPHL = (1.7 ns/pF) CL + 215 ns |
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5.0 |
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Ð |
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280 |
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560 |
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tPLH, tPHL = (0.66 ns/pF) CL + 97 ns |
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10 |
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115 |
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tPLH, tPHL = (0.5 ns/pF) CL + 75 ns |
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15 |
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Reset to Q |
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tPHL |
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ns |
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tPHL = (1.7 ns/pF) CL + 265 ns |
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5.0 |
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330 |
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650 |
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tPHL = (0.66 ns/pF) CL + 117 ns |
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10 |
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tPHL = (0.66 ns/pF) CL + 95 ns |
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Clock Pulse Width |
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tw(H) |
5.0 |
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200 |
100 |
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ns |
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tw(L) |
10 |
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100 |
50 |
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Clock Pulse Frequency |
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fcl |
5.0 |
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2.5 |
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1.5 |
MHz |
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3.0 |
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8.0 |
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4.0 |
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Clock or Enable Rise and Fall Time |
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tTHL, tTLH |
5.0 |
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15 |
μs |
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4 |
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Enable Pulse Width |
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tWH(E) |
5.0 |
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440 |
220 |
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Ð |
ns |
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10 |
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200 |
100 |
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15 |
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140 |
70 |
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Reset Pulse Width |
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tWH(R) |
5.0 |
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280 |
125 |
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Ð |
ns |
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10 |
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120 |
55 |
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15 |
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90 |
40 |
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Reset Removal Time |
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trem |
5.0 |
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± 5 |
± 45 |
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Ð |
ns |
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10 |
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15 |
± 15 |
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15 |
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20 |
± 5 |
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* The formulas given are for the typical characteristics only at 25_C. |
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||||||||||||||||||||||||||||||||
#Data labelled ªTypº is not to be used for design purposes but is intended as an indication of the IC's potential performance. |
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500 μF |
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VDD |
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0.01 μF |
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I |
D |
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CERAMIC |
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PULSE |
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C |
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Q0 |
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GENERATOR |
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Q1 |
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E |
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Q2 |
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CL |
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Q3 |
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C |
L |
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R |
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CL |
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CL |
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20 ns |
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VSS |
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20 ns |
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90% |
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50% |
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10% |
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VSS |
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VARIABLE |
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WIDTH |
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||||
Figure 1. Power Dissipation Test Circuit and Waveform
MOTOROLA CMOS LOGIC DATA |
MC14518B MC14520B |
|
411 |
PULSE
GENERATOR
|
VDD |
20 ns |
|
20 ns |
VDD |
|
|
|
|
90% |
|
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|
CLOCK |
|
50% |
|
C |
Q0 |
INPUT |
|
10% |
VSS |
|
tWH |
tWL |
|||
|
Q1 |
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Q2 |
|
tPLH |
tPHL |
|
E |
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CL |
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Q3 |
CL |
90% |
|
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R |
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50% |
|||
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CL |
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||
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CL |
Q |
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10% |
|
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VSS |
|
tf |
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|
tr |
|
Figure 2. Switching Time Test Circuit and Waveforms
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
CLOCK
ENABLE
RESET
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
0 |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
0 |
Q0
Q1
MC14518B
Q2
Q3
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
0 |
1 |
2 |
3 |
4 |
Q0
Q1
MC14520B
Q2
Q3
Figure 3. Timing Diagram
MC14518B MC14520B |
MOTOROLA CMOS LOGIC DATA |
412 |
|
|
Q0 |
|
Q1 |
|
Q2 |
|
Q3 |
D |
Q |
D |
Q |
D |
Q |
D |
Q |
C R Q |
C R Q |
C R Q |
C R Q |
||||
RESET |
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ENABLE |
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CLOCK |
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Figure 4. Decade Counter (MC14518B) Logic Diagram
(1/2 of Device Shown)
|
Q0 |
|
Q1 |
|
Q2 |
|
Q3 |
D |
Q |
D |
Q |
D |
Q |
D |
Q |
C R Q |
C R Q |
C R Q |
C R Q |
||||
RESET |
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ENABLE |
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CLOCK |
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Figure 5. Binary Counter (MC14520B) Logic Diagram
(1/2 of Device Shown)
MOTOROLA CMOS LOGIC DATA |
MC14518B MC14520B |
|
413 |